Chaired by Andreas Burg (EPFL)
Compressive sensing (CS) is a promising solution for physiological signal acquisition in wireless healthcare systems. It enables new reduced-complexity designs of sensor nodes and helps to save overall transmission power in the wireless sensor network. Many CS-related sensors and reconstruction chips had been developed over past years. However, compared with the small sensor nodes, the reconstruction cost of the CS signals becomes dominant. Reconstructing all received CS signals becomes another significant overhead and bottleneck before they are sent to machine learning (ML) algorithms for data analytics. In this talk, we introduce a new design framework called Compressive Analytics (CA). By extracting the deterministic information of the CS signals, we can perform data analytics directly in the compressed domain “without” reconstructing the received CS signals. There are two advantages: Firstly, we can avoid the costly CS reconstruction operations at the receiver side. Secondly, we can perform the ML algorithm (e.g., SVM) in the compressed domain (in a much smaller dimension), rather than in the original signal domain, resulting in low-complexity ML. We exemplify the proposed CA by using two design cases. The first one is detecting Atrial Fibrillation (AF) from CS-compressed ECG signals. The overall parameters and multiplications are only 5% compared with the conventional “Reconstruction Learning (RL)” mechanism (Reconstruction followed by ML). The second one is compressed-domain ECG-based user identification. The ECG signal is a natural biometric that be measured continuously and transmitted over wireless channels. In certain extreme environments like clean room, it becomes the only viable solution for continuous biometric user identification. We will show a live demo of the proposed CS-domain ECG-based user identification by using MediaTek’s Sensio watch. The topics presented in this talk demonstrate the feasibility of linking CS directly with ML while bypassing the expensive CS reconstruction stage. They are applicable to CS-based wireless healthcare systems when extreme light-weight and low-power detection of physiological signals is in demand.
An-Yeu (Andy) Wu (IEEE M’96-SM’12-F’15) received the B.S. degree from National Taiwan University in 1987, and the M.S. and Ph.D. degrees from the University of Maryland, College Park in 1992 and 1995, respectively, all in Electrical Engineering.
In August 2000, he joined the faculty of the Department of Electrical Engineering and the Graduate Institute of Electronics Engineering, National Taiwan University (NTU), where he is currently a Professor. His research interests include low-power/high-performance VLSI architectures for DSP and communication applications, adaptive/bio-medical signal processing, reconfigurable broadband access systems and architectures, and System-on-Chip (SoC)/Network-on-Chip (NoC)/AI platform for software/hardware co-design. He has published more than 280 refereed journal and conference papers in above research areas, together with six book chapters and 24 granted US patents.
From August 2007 to Dec. 2009, he was on leave from NTU and served as the Deputy General Director of SoC Technology Center (STC), Industrial Technology Research Institute (ITRI), Hsinchu, TAIWAN, supervising WiMAX, Parallel Core Architecture (PAC) VLIW DSP Processor, and Android-based Multicore SoC platform projects. From March 2014 to September 2017, Dr. Wu was the Director of national talent cultivation program office in National Program for Intelligent Electronics (NPIE), under sponsorship of Ministry of Education in Taiwan.
In 2015, Prof. Wu was elevated to IEEE Fellow for his contributions to “DSP algorithms and VLSI designs for communication IC/SoC”. He received 2019 ECE Distinguished Alumni Award from ECE department of University of Maryland (UMD), and 2019 Outstanding Engineering Professor Award, from the Chinese Institute of Engineers (CIE), Taiwan. From August 2016 to July 2019, he served as the Director of Graduate Institute of Electronics Engineering (GIEE), National Taiwan University. He now serves as a Board of Governor (BoG) Member in IEEE Circuits and Systems Society (CASS) for two terms (2016-2018, 2019-2021). Prof. Wu also serves as Editor-in-Chief (EiC) of IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) since 2020.